Discrete RF power LDMOS transistors are primarily used for building power amplifiers used in radio base stations.
A top view of a portion of the layout of a traditional RF power LDMOS transistor is illustrated in FIG. 1. The transistor comprises a number of parallel LDMOS transistor cells, two of which are shown in FIG. 1, where the cells are an interdigitated finger structure containing pairs of drain fingers 1, pairs of gate fingers 2 and source/bulk metal clamps 3. The drain fingers 1 and the gate fingers 2 are connected to a drain feeder bar 4 and a gate feeder bar 5, respectively, on opposite sides of the transistor cells as shown in FIG. 1. Traditional LDMOS Power transistors comprise a number of parallel cells.
However, third generation (3G) wireless systems set new demands on RF power transistors. Not only higher frequency (>2 GHz), which in itself is a challenge, but extreme demands on linearity has compelled designers of power amplifiers to use power transistors way below their rated maximum output power. It is at this backed off output power level the transistors must perform, i.e. have high gain and good efficiency.
These new demands have forced RF power transistor designers to leave the old “parallel cells” layout of the transistors and switch to a slightly different design. The 3G design uses only one interdigitated transistor cell, rotated 90 degrees compared to the orientation of the cells in the older design.
The largest benefit with this new design is a considerably reduced transistor periphery per active transistor area, which in turn results in lower output capacitance and improved efficiency.
In order to make the gate periphery equal to a transistor with multiple parallel cells, the single cell needs to be stretched in both dimensions, so that it contains many more fingers. In order to keep a decent aspect ratio of the transistor die, the fingers also need to be much longer.
The principle for the 3G design is shown in FIG. 2 which is a top view of a portion of the layout of a known 3G RF power LDMOS transistor. Pairs of drain fingers 6, of which only one pair is shown in FIG. 2, are connected to a common drain bond pad (not shown). Pairs of gate fingers 7, of which only one pair is shown in FIG. 2, are interconnected at their ends and at predetermined positions along their lengths by pieces of a first metal layer. One such interconnection piece 8 is shown in FIG. 2. Source/bulk metal clamps 9, also produced from said first metal layer, extend over the pair of gate fingers 7 between the interconnection pieces.
As described above, the 3G design is unavoidably associated with longer fingers. This is a problem especially on the gate side of the transistor. The gate fingers are usually made of highly doped polysilicon, possibly with a layer of metal silicide on top, in order to reduce the resistivity. However, the resistance in the gate fingers is far from negligible, and at some point the length of the gate fingers will affect transistor performance negatively.
The way this problem has been solved in the known 3G design of the transistor is by introducing a second metal layer. By doing this, one can design a metal runner 10 on top of the source/bulk clamps 9. The metal runner 10 is isolated from the clamps 9 by a dielectric layer (not shown in FIG. 2), and is connected to the pair of gate fingers 7 at predetermined positions along the length of gate fingers 7 via the interconnection piece 8 as well as at their respective ends. One end of the metal runners 10 is connected to a common gate bond pad (not shown).
Hereby, the effective length of each gate finger will be equal to half the distance between two gate interconnection pieces.
However, the introduction of the second metal layer in the transistor design adds complexity both to the design and to the production process. In this connection, it should be pointed out that in FIG. 2, the drain fingers 6 are made up of two metal layers, namely the second metal layer on top of the first metal layer. Two extra mask steps together with a number of extra process steps need to be added to the production process of the transistor die.